The present invention relates to integrated circuit devices, and more particularly, to methods and structures for testing integrated memory arrays.
Various types of defects and failures can occur during the manufacture of semiconductor devices. A xe2x80x9cfailurexe2x80x9d occurs when a semiconductor device fails to meet specifications. A xe2x80x9cdefectxe2x80x9d occurs when a semiconductor device has an improper circuit structure that currently presents a failure of the device, or has the potential to cause failure during the expected lifetime of the device. In a memory device for example, manufacturing errors may produce a polysilicon residue or xe2x80x9cstringerxe2x80x9d between a pair of adjacent memory cells. The stringer provides a current path between the adjacent cells so that a xe2x80x9clowxe2x80x9d voltage written to one cell lowers a xe2x80x9chighxe2x80x9d voltage on the adjacent cell to a high value, resulting in incorrect data being stored in the memory device.
Testing is performed on semiconductor devices to locate such defects and failures. As circuit density on semiconductor devices increases, the number of defects and failures can increase. Semiconductor manufacturers, therefore, have an increasing need to detect defects and failures in semiconductor devices.
Dynamic random access memory devices (xe2x80x9cDRAMsxe2x80x9d) are one type of device on which such tests are performed. DRAMs typically include one or more arrays of memory cells that are each arranged in rows and columns. Word or row lines extend along each of the rows to enable all of the memory cells along the row. Bit, digit, or column lines (or pairs of lines) extend along the columns of the array to select individual memory cells along a row which data is to be read from or written to.
During testing, predetermined data or voltage values are applied to selected row and column addresses, that correspond to certain memory cells to store or xe2x80x9cwritexe2x80x9d data in the cells. Then, voltage values are read from such memory cells to determine if the data read matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects, and the semiconductor devices fail the test.
A person testing the several die on the wafer can then examine a particular die by means of a microscope to determine if failures occurred from masking defects, during the deposition of certain layers, and so forth. During the initial development of a semiconductor device, and while the device is in die form, changes to masks or the fabrication process can be made to compensate for most detected failures. Once a semiconductor device is in production and packaged as a chip, redundant circuitry on the semiconductor device can be employed to replace certain failed components. Such redundant circuitry cannot replace all failed components, and therefore, some failed devices must generally be discarded.
To increase output of acceptable devices, semiconductor manufacturers try to rapidly test the devices for defects before shipping them to a vendor or user. The semiconductor devices are often tested by automated testing circuitry that applies predetermined voltages and signals to the chip, writes test patterns to the chip, and analyzes the results therefrom to detect failures in the chip.
Returning to the above-described problem of stringers between adjacent cells, the conductive path formed by such stringers may have a high resistance. The low voltage on a first cell will then take an extended period to decrease the voltage of an adjacent second cell. Therefore, such intercell defects may not be revealed by tests that read the voltage of the second cell shortly after writing voltage to the first cell. As a result, after applying a voltage to the first cell, automated testing circuitry must wait before looking for voltage changes at the adjacent cell. Typical wait times, or xe2x80x9ctesting intervals,xe2x80x9d between writing to the first cell and reading from the second cell are 48-64 msec. If such a procedure were applied sequentially to each cell in the memory array, testing of devices would take over 10 hours for every million cells. The cost of such testing would be prohibitive.
One approach to reducing the time for testing such devices is to prewrite an entire row of the memory array to logic states such that all of the cells in the first row are at a high voltage Vxe2x80x2HIGH that is equal to the supply voltage VCC. Then, an adjacent row is written to logic states such that all of the cells in the adjacent row are at low voltages Vxe2x80x2LOW that are equal to a reference voltage VREF. Then, after the testing interval, the data in the second row are read to see if any current leakage has caused changes in the cell voltages.
During the testing interval, the charge leaking from the first row""s cells must be removed from cells in the second row, as will now be explained with reference to FIG. 1. As shown by the upper broken line in FIG. 1, if the leaking charge is not removed, the voltage Vxe2x80x2LOW of the low voltage cell will rise as the voltage Vxe2x80x2HIGH of the high voltage cell rises. The two voltages will asymptotically approach a voltage DVC2 which is approximately halfway between VCC and VREF, assuming equal capacitances of the cells. As a result, the low voltage cell remains below the voltage DVC2 and the high voltage cell remains above the voltage DVC2. When the high voltage cell is coupled to its respective digit line (which is precharged to DVC2) for reading, the high voltage Vxe2x80x2HIGH will pull the digit line up. A sense amplifier coupled between the digit line and an adjacent complementary digit line will read the data as unchanged, even though a stringer is present. Consequently, the defect will not be identified.
To overcome this problem, the second word line remains active over the first testing interval. Because the second word line is active, the low digit lines (kept low by the sense amplifiers) remove any charge leaking from the cells in the first row, and as represented by the solid line in FIG. 1, the voltage VLOW of the low voltage cell remains low. The voltage VHIGH of the high voltage cell falls asymptotically toward VREF and eventually becomes less than the voltage DVC2.
At the end of the testing interval, the second row is deactivated to isolate the cells from the digit lines and the digit lines are equilibrated. Then, data are read from the cells of the first row.
If stringers couple any of the originally activated cells of the first row to the cells in the second row, the cells in the first row will discharge to a low state. Consequently, one or more cells in the first row will contain incorrect data. Therefore, the data read from the first row will indicate the presence or absence of intercell defects.
After data are read from the first row, data are written to all of the cells in third and fourth rows so that the cells contain opposite voltage levels. The third row is then read to set the digit line voltages. Again, the word lines remain ON for the entire testing interval to keep the high voltage cells coupled to the digit lines. After the testing interval, the third row is turned OFF and data are read from the cells in the fourth row to see if all of the data are unchanged. The above-described process is repeated until all of the rows of the array have been either written to or read from.
In the above-described process, all of the even rows (starting from row 0) are activated and all of the odd rows are read. This process test of intercell defects between only half of the adjacent row combinations. For example, the process does not identify intercell defects between the second and third rows. Therefore, the process is typically repeated by writing data to all of the odd rows and reading data from the immediately subsequent even rows.
For a memory array having 4,096 rows and using 64 msec intervals, each of the above-described passes would take at least 131.07 secs. The overall time to test all of the rows is then at least 262.14 secs, or over four minutes per memory array. While the time savings in the above approach are significant as compared to the approach of individually activating each cell in sequence, a testing time of over four minutes per part is significant. Also, this time roughly doubles when an analogous test procedure is applied to detect intercell defects between columns, assuming a 4096 by 4096 array (ie., a 16 M bit device). Moreover, the time consumption will continue to increase as the number of cells in the memory array increase.
A method and structure for identifying intercell defects in a memory array raises a plurality of cells along a first digit line to a first voltage and couples a plurality of cells along a complementary digit line to a second voltage. A plurality of word lines are then activated to sustain the voltages of the cells along the first digit line during a testing interval. At the end of the testing interval, data are read from the cells along the second digit line to see if any of the voltages have changed due to leakage through an intercell defect.
In one embodiment of the invention, the memory includes a memory array that is initially written to a checkerboard pattern. Then, a first word line is activated to couple cells in a first row to respective digit lines. Next, sense amplifiers are activated to sustain the voltages of the digit lines while selected additional word lines are activated. In one embodiment, every other word line is activated. In another embodiment, every fourth word line is activated. The word lines remain active over the entire testing interval so that the sense amplifiers can replace charge that leaks from any of the cells. After a selected testing interval the word lines are deactivated, the digit lines are equilibrated and data are read from cells of inactivated rows to see if any of the data have changed.
One embodiment according to the invention includes a biasing circuit that can selectively drive all of the digit lines to a low voltage. Because both the digit lines D, {overscore (D)} in each complementary pair are at a high voltage, cells in the original checkerboard pattern are not pulled low when the corresponding word lines are activated.
One embodiment of the biasing circuit includes an input logic circuit that receives three logic signals and outputs three control voltages in response. The control voltages drive gates of respective transistors, each coupled to a common node in a precharge circuit. The transistors respond to the control voltages by providing high voltage, precharge voltage or ground to the common node. The precharge circuit then couples the common node to the digit lines to set the digit line voltages.